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IXDN430 / IXDI430 / IXDD430 / IXDS430
Pin Configurations
Vcc 1
Vcc 2
Vcc 3
Vcc 4
28 Vcc
27 Vcc
26 Vcc
25 Vcc
N/C 5
UVSEL 6
N/C 7
IN 8
EN 9
28 Pin SOIC
(SI-CT)
24 OUT P
23 OUT P
22 OUT P
21 OUT N
20 OUT N
1
2
3
4
5
Vcc
OUT
GND
IN
EN *
INV 10
19 OUT N
GND 11
GND 12
GND 13
GND 14
Pin Description
18 GND
17 GND
16 GND
15 GND
TO220 (CI)
TO263 (YI)
SYMBOL
VCC
IN
EN *
INV
OUT P
OUT N
GND
UVSEL
FUNCTION
Supply Voltage
Input
Enable
Invert
Output
Ground
Select Under
Voltage Level
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 8.5V to 35V.
Input signal-TTL or CMOS compatible.
The system enable pin. This pin, when driven low, disables the chip,
forcing high impedance state to the output (IXDD430 Only).
Forcing INV low causes the IXDS430 to become non-inverted, while
forcing INV high causes the IXDS430 to become inverted.
Respective P and N driver outputs. For application purposes this pin
is connected, through a resistor, to Gate of a MOSFET/IGBT. The P
and N output pins are connected together in the TO-263 and TO-220
packages.
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
W ith UVSEL connected to Vcc, IXDS430 outputs go low at Vcc <
8.5V; W ith UVSEL open, under voltage level is set at Vcc < 12.5V
* This pin is used only on the IXDD430, and is N/C (not connected) on the IXDI430 and IXDN430.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when
handling and assembling this component.
Figure 2 - Characteristics Test Diagram
.
Vcc
.
Vcc
C
BYPASS/
FILTER
+
-
C LOAD
OUT
GND IXDD430
IN
+
-
Vin
5
EN
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